1. Field of the Invention
The present invention relates to Aluminum (Al), Gallium (GA), Indium (In) N-based compound semiconductor device and a method of fabricating the same, and more particularly to a (Al, Ga, In)N-based compound semiconductor device comprising a (Al, Ga, In)N-based compound semiconductor layer (P layer) including P type impurities and a transparent electrode provided on the P layer, and a method of fabricating the (Al, Ga, In) N-based compound semiconductor device.
2. Discussion of the Background
A (Al, Ga, In)N-based compound semiconductor is applied, for example, to a compound semiconductor device such as a light emitting diode (LED) or a laser diode (LD). FIG. 1 is a cross-sectional view schematically showing a conventional (Al, Ga, In)N-based compound semiconductor device.
Referring to FIG. 1, a (Al, Ga, In)N-based compound semiconductor layer (N layer) 13 including N type impurities, an active layer 15 and a (Al, Ga, In)N-based compound semiconductor layer (P layer) 17 including P type impurities are sequentially formed on a substrate 11. The P layer 17, the active layer 15 and the N layer 13 are partially etched such that the N layer 13 is partially exposed to the outside. Electrodes 19 and 21 including Ni and Au are formed on the P layer 17, and an electrode 25 is also formed on the N layer 13.
Generally, impurities are doped in the P layer 17 to secure the conductivity in the conventional (Al, Ga, In)N-based compound semiconductor device 101. However, the P type impurities, e.g., magnesium (Mg), do not fulfill the function as an electron acceptor that provides free holes, since they are easily bonded with hydrogen (H) existing in a growth chamber. Therefore, an additional annealing process of disconnecting bonds between the P type impurities and hydrogen is performed in a process of fabricating a P layer of a (Al, Ga, In)N-based compound semiconductor.
FIG. 2 is a flowchart illustrating a method of fabricating a P layer of a conventional (Al, Ga, In)N-based compound semiconductor.
Referring to FIG. 2, P type impurities and source gases for the compound semiconductor are supplied to a growth chamber such that a P layer of the compound semiconductor is grown on a substrate (P1). After the full growth of the P layer, the growth chamber is cooled to lower the temperature of the substrate (P2). Thereafter, the P layer-grown substrate is withdrawn from the growth chamber (P3). Then, annealing is performed for the P layer (P4). Referring to U.S. Pat. No. 5,306,662, a P layer of a compound semiconductor is grown using P type impurities and source gases for the compound semiconductor and the P layer is subsequently annealed at a temperature of 400° C. or more. As a result, hydrogen bonded to the P type impurities is removed to form a P type (Al, Ga, In)N-based compound semiconductor with low and uniform resistance.
Meanwhile, an annealing process is also performed to obtain ohmic contact characteristics between the P layer and a metallic electrode. With the annealing process, there are advantages in that good ohmic contact characteristics between the electrode and the P layer is obtained, and bonds between the P type impurities and hydrogen remaining in the P layer are disconnected.
In such a conventional (Al, Ga, In)N-based compound semiconductor device, at least one annealing process should be performed to lower the resistance of the P layer or improve ohmic contact characteristics between the P layer and a transparent electrode. However, the annealing process has a problem in that it makes a fabrication process of a compound semiconductor device complicated and troublesome. The annealing process prolongs fabrication time of a product and particularly increases the unit cost of a product since expensive equipment for performing the annealing process should be purchased, and a space for installing the equipment is required, resulting in increases of investment costs for fabrication facilities.